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winbond expresscard? power interface switch W83L351 series
W83L351 series W83L351 series data sheet revision history no pages dates version version on web main contents 1 . a l l a p r . / 0 7 1 . 0 n . a all versions before 1.0 are preliminary versions. 2 28 july 5, 2007 1.1 update the ordering information and add the taping spec. 3 4 5 6 7 publ i c at i on dat e : jul y 5, 2007 -i- revision 1.10
W83L351 series table of contents- 1. features ....................................................................................................................... .......... 1 2. pin configuration a nd descript ion ............................................................................ 2 3. application circui t ............................................................................................................ .5 4. internal block diagram ................................................................................................... 6 5. absolute maximu m ratings ............................................................................................. 7 6. recommended operatin g conditi ons ......................................................................... 8 7. electrical chara cteristics ........................................................................................... 9 8. switching chara cteristi cs .......................................................................................... 12 9. functional trut h tables ............................................................................................... 13 10. typical operatin g wavefor ms .................................................................................... 15 11. expresscard timing diagrams ..................................................................................... 20 12. package dime nsion ........................................................................................................... 24 13. ordering info rmation .................................................................................................... 28 14. top marking spec ification ............................................................................................ 29 -ii-
W83L351 series 1. features ? ? ? ? ? ? ? ? ? publ i c at i on dat e : jul y 5, 2007 -1- revision 1.10
W83L351 series 2. pin configuration and description W83L351g (top view) W83L351yg W83L351ycg ( to p view ) 6 7 8 9 1 0 2 0 1 9 1 8 1 7 1 6 15 14 13 12 11 1 2 3 4 5 aux o ut nc nc 1.5vin 1.5vout st by# 3.3vin 3.3vout nc nc c p p e # c p u s b # p e r s t # g n d s y s r s t # n c a u x i n r c l k e n o c # s h d n # 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 sysrst # shdn# st by# 3.3vin 3.3vin 3.3vout 3.3vout perst # nc gnd oc# rclken aux i n aux o ut 1.5vin 1.5vin 1.5vout 1.5vout cppe# cpusb# pin symbol g yg ycg i/o function s y s r s t # 1 6 i (*) system reset input ? active low, logic level signal. internally pulled up to auxin. this input is driv en by the host system and directly affec t s perst#. as s e rting sysrst# (logic low) forc es perst# to as s e rt. rclken is not affec t ed by the as s e rtion of sysrst#. s h d n # 2 20 i (*) shutdown input ? active low, logic level signal. internally pulled up to auxin. when asserted (logic low) , this input instructs the power switch to turn off all voltage outputs and the discharge fets are activated. -2-
W83L351 series continued pin symbol g yg ycg i/o function s t b y # 3 1 i (*) standby input ? active low, logic level signal. internally pulled up to auxin. when asserted (logic low) a fter the card is inserted, this input places the power switch in standby mode by turning off the 3.3v and 1.5v power switches and keeping the aux switch on. if the signal is asserted prior to the card being present, stby# places the power switch in off m ode by turning off the aux, 3.3v, and 1.5v power switches. p e r s t # 8 8 o a logic level power good (with delay). when powered up, this output remains asserted (logic level low) until all power rails are within the tolerance. once all power rails are within the tolerance and rclken has been released (logic high), perst# is de- asserted (logic high) after a time delay, as shown in the parametric table. when powered down, this output is asserted whenever any of the power rails drops bel ow their voltage tolerance. the perst# signal is an output fr om the host system and an input to the expresscard module. this signal is only used by pci express-based modules and its function is to place the expresscard module in a reset state. during power up, power down, or whenever power to the expresscard module is not stable or not within voltage tolerance limits, the expresscard st andard requires that perst# be asserted. as a result, this signal also serves as a power-good indicator to the expresscard m odule, and the relationship between the power rails and perst# are explicitly defined in the expresscard standard. the host can also place the expresscard module in a reset state by as s e rting a s y s t em res e t sysrst#. this s y s t em res e t generates a perst# signal to t he expresscard module without disrupting the voltage rails. this is normally called a warm reset. however, in a cold start situati on, the system reset can also be used to prolong the assertion time of perst#. c p u s b # 1 1 9 i (*) card present input for usb cards. internally pulled up to auxin. a logic low level on this input indicates that the card present supports the usb functions. when a card is inserted, cpusb# is physically connected to ground if the ca rd supports usb functions. c p p e # 1 2 10 i (*) card present input for pci express cards. internally pulled up to auxin. a logic low level on this input indicates that the card present supports the pci expre ss functions. when a card is inserted, cppe# is physically connected to ground if the card supports pci express functions. publ i c at i on dat e : jul y 5, 2007 -3- revision 1.10
W83L351 series continued pin symbol g yg ycg i/o function r c l k e n 1 9 18 i (*) /o reference clock enable signal. as an output, it is a logic level power good to the host (no delay ? open drain). as an input, if the signal is kept inactive (low) by the host, perst# will be prevented from being de-asserted. internally pulled up to auxin. this pin serves both as an input and an output. when powered up, a discharge fet keeps this signal at a low state as long as any of the output power rails is out of thei r tolerance range. once all output power rails are within the toler ance, the switch releases rclken, allowing it to transit to a high state (internally pulled up to auxin). the transition of rclken from a low to a high state starts an internal timer for the purpose of de-asserting perst#. as an input, rclken can be kept low to delay the start of the perst# internal timer. because rclken is inte rnally connected to a discharge fet, this pin can only be driven low and should never be driven high as a logic input. when an external circuit drives this pin low, rclken becomes an input; otherwi se, this pin is an output. o c # 2 0 19 o d over current status output (open drain). this pin is an open-drain output. when any of the three pow er switches (aux, 3.3v, and 1.5v) is in an over current conditi on, oc# is asserted (logic low) by an internal discharge fet with a deglitch delay. otherwise, the discharge fet is open, and the pin can be pulled up to a power supply through an external resistor. 3.3vin 4, 5 2 i primary voltage source, 3.3v input for 3.3vout 1.5vin 15,16 12 i secondary voltage s ource, 1.5v input for 1.5vout auxin 18 17 i auxiliary voltage source, aux input for auxout and chip power. 3 . 3 v o u t 6 , 7 3 o switched output that delivers 0v , 3.3v or high impedance to the card. 1.5vout 13, 14 11 o switched output that delivers 0v , 1.5v or high impedance to the card. a u x o u t 1 7 15 o switched output that delivers 0v , aux or high impedance to the card. g n d 1 0 7 3 g r o u n d n c 9 4, 5, 13, 14, 16 n o c o n n e c t i o n notice: (*) be aware that no input pins can be driven high before the auxiliary voltage is valid. -4-
W83L351 series 3. application circuit c1 2 22u pe r s t # 1. 5v ou t s y sr st # au x o u t c3 0. 1u c7 0. 1u c1 0. 1u 1. 5v ou t 3. 3v i n st by # 3. 3v ou t c8 22u c9 0. 1u cp us b # au x o u t c6 4. 7u c5 0. 1u c4 22u 1. 5v i n u1 w 8 3l351 g 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 sy sr s t # s hdn# st by # 3. 3v i n 3. 3v i n 3. 3v ou t 3. 3v ou t pe r s t # nc gn d oc # rc l k e n au x i n au x o u t 1. 5 v i n 1. 5 v i n 1. 5 v o u t 1. 5 v o u t cp p e # cp us b # au x i n sh d n # au x i n cp p e # c1 0 4. 7u 3. 3v i n c1 1 0. 1u 3. 3 v ou t r1 2k 1. 5v i n rcl k e n au x i n c2 4. 7u c1 0. 1u au x o u t c1 2 22 u cp us b # 1. 5 v o u t 3. 3v i n au x o u t r1 2k c8 22 u rcl k e n c2 4. 7u c7 0. 1u u1 w 8 3l 351 y g / y c g 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 st b y # 3. 3vi n 3. 3vou t nc nc sy sr s t # gn d pe r s t # cp us b # cp p e # au x o u t nc nc 1. 5vi n 1. 5vou t s hdn# oc # rcl k e n au x i n nc cp p e # s hdn# 3. 3v ou t 1. 5 v i n c1 0 4. 7u c5 0. 1u au x i n c1 1 0. 1u st b y # c4 22 u 3. 3v i n c9 0. 1u s y sr st # pe r s t # 3. 3v ou t 1. 5v ou t 1. 5v i n c3 0. 1u au x i n c6 4. 7u publ i c at i on dat e : jul y 5, 2007 -5- revision 1.10
W83L351 series 4. internal block diagram ??33?? ??3? ?????3?? ?? ?? ?? ?? ?? ? ? ?a? ? aa?? ? ?? ?? ????3? ????3? ???3? ??3? ?3 ??a? ??a? ?a? a?3? ???t? ?????3? ?????3? ?? ?? -6-
W83L351 series 5. absolute maximum ratings item symbol rating unit v i(3.3vin) -0.3 to 6 v v i(1.5vin) -0.3 to 6 v input voltage v i(auxin) -0.3 to 6 v logic input/output voltage -0.3 to 6 v v o(3.3vout ) -0.3 to 6 v v o(1.5vout ) -0.3 to 6 v output voltage v o(auxout ) -0.3 to 6 v i o(3.3out ) i n t e r n a l l y l i m i t e d i o(1.5out ) i n t e r n a l l y l i m i t e d output current i o(auxout ) i n t e r n a l l y l i m i t e d operating temperature range t opt 0 to 70 human body mode 2 kv machine mode 200 v electrostatic discharge protection latch-up 100 ma
W83L351 series 6. recommended operating conditions item min max unit v i(3.3vin) 3.3vin is only required for its respective functions 3 3 . 6 v i(1.5vin) 1.5vin is only required for its respective functions 1 . 3 5 1 . 6 5 input voltage v i(auxin) auxin is required for all circuit operations 3 3.6 v i o(3.3vout ) 0 1.3 a i o(1.5vout ) 0 650 ma continuous output current i o(auxout ) tj=120 0 2 7 5 ma -8-
W83L351 series 7. electrical characteristics t a = 25 ? publ i c at i on dat e : jul y 5, 2007 -9- revision 1.10
W83L351 series continued paramet er test conditions min t yp max unit i i(auxin) 1 6 0 2 1 0 i i(3.3vin) 6 1 0 standby mode (3) i i(1.5vin) cpusb# = cppe# = 0 v 1.5vin = 0 v (include cppe# and cpusb# logic pull-up currents) 0 0 . 1 ua i i(auxin) 2 2 5 0 i i(3.3vin) 0 5 0 i lkg(fw d) forward leakage current i i(1.5vin) shdn# = 3.3 v, cpusb# = cppe# = 3.3 v (no c a rd present, discharge fets are on);current measured at input pins, includes rclken pull- up current 0 5 0 ua logic section (sysrst, shdn#, stby#, perst#, rclken , oc#, cpusb#, cppe#) sysrst# = 3.6 v, s i nk ing 0 i (sy s rs#) i n p u t sysrst# = 0 v, s ourc i ng 10 17. 5 30 ua shdn# = 3.6 v, sinking 0 i (shdn#) i n p u t shdn# = 0 v, sourcing 10 17. 5 30 ua stby# = 3.6 v, sinking 0 i (st b y # ) i n p u t stby# = 0 v, sourcing 10 17. 5 30 ua i (rclken ) input rclken = 0 v, sourcing 10 18 30 ua cpusb# or cppe# = 0 v, sinking 0 logic input supply current i (cpusb#) or i (cppe#) inputs cpusb# or cppe# = 3.6 v, sourcing 10 17. 5 30 ua high level 2 logic input voltage low level 0.8 v rclken output low voltage output io(rclken) = 60 a 0.4 v 3.3vout falling 2.7 3 auxout falling 2.7 3 perst# assertion threshold of output voltage (perst# asserted when any output voltage falls below the threshold) 1.5vout falling 1.2 1.5 v perst# assertion delay from output voltage 3.3vout, auxout, 1.5vout falling 5 0 0 n s perst# de-assertion delay from output voltage 3.3vout, auxout, or 1.5vout rising within tolerance 1 2 0 m s -10-
W83L351 series continued paramet er test conditions min t yp max unit p e r s t # a s s e r t i o n d e l a y f r o m sysrst# max time from sysrst asserted 2 5 500 n s t w ( perst #) perst# minimum pulse width 3.3vout, auxout, or 1.5vout falling out of tolerance or triggered by sysrst# 1 0 0 3 4 0 u s perst# output low voltage 0.4 v perst# output high voltage i o(perst #) = 500 a 2.4 v oc# output low voltage i o(oc#) = 2 ma 0.4 v oc# deglitch falling into or out of an over current condition 2 0 m s undervolta ge lockout (uvlo) 3.3vin uvlo 3.3vin level, below which 3.3vin and 1.5vin switches are off 2 . 6 2 . 9 1.5vin uvlo 1.5vin level, below which 3.3vin and 1.5vin switches are off 1 . 0 1 . 2 5 auxin uvlo auxin level, below which all switches are off 2 . 6 2 . 9 v uvlo hysteresis 100 mv note 1: in the shutdow n mode or the standby mode (1), the auxin quiescent current includes a normal operation current, shdn# or stby # internal pull-up current and rclken inter nal pull-up current. in the standby modes (2) & (3), the auxin quiescent current includes a normal operati on current and a rclken internal-up current. publ i c at i on dat e : jul y 5, 2007 -11- revision 1.10
W83L351 series 8. switching characteristics t a = 25 , v i ( 3 .3vin) = v i ( a ux in) = 3.3 v, v i ( 1 .5vin) = 1.5 v, v i (s hdn# ) , v i (s t b y# ) = 3.3 v, v i ( c ppe#) = v i ( c pu sb#) = 0 v , v i ( s y s rst ) = 3.3 v, oc# and rclken and perst# are open, all voltage outputs unloaded (unless otherwise noted) parameter test conditions min t yp max unit 3.3vin to 3.3vout c l( 3.3vou t ) = 0 .1uf , i o( 3.3vout )= 0 a 0 . 1 6 auxin to auxo ut c l( au x v ou t )= 0.1uf , i o( aux o ut ) = 0 a 0 . 1 6 1.5vin to 1.5vout c l( 1.5vou t ) = 0 .1uf , i o( 1.5vout ) = 0 a 0 . 1 6 3.3vin to 3.3vout c l( 3.3vou t ) = 100uf , r l =v i( 3.3vin ) / 1 a 0 . 1 6 auxin to auxo ut c l( au x v ou t ) = 100uf , r l =v i(a u xinin) /0.250a 0 . 1 6 t r output rise times 1.5vin to 1.5vout c l( 1.5vou t ) = 100uf , r l =v i( 1.5vin ) /0.500a 0 . 1 6 ms 3.3vin to 3.3vout c l( 3.3vou t ) = 0 .1uf , i o( 3.3vout )= 0 a 1 0 1 5 0 auxin to auxo ut c l( au x v ou t )= 0.1uf , i o( aux o ut ) = 0 a 1 0 1 5 0 1.5vin to 1.5vout c l( 1.5vou t ) = 0 .1uf , i o( 1.5vout ) = 0 a 1 0 1 5 0 us 3.3vin to 3.3vout c l( 3.3vou t ) = 20uf , i o( 3.3vout )= 0 a 5 3 0 auxin to auxo ut c l( au x v ou t ) = 20uf , i o( aux o ut ) = 0 a 5 3 0 t f output fall times w hen card removed (both cpusb# and cppe# de- asserted) 1.5vin to 1.5vout c l( 1.5vou t ) = 20uf , i o( 1.5vout ) = 0 a 5 3 0 ms 3.3vin to 3.3vout c l( 3.3vou t ) = 0 .1uf , i o( 3.3vout )= 0 a 1 0 1 5 0 auxin to auxo ut c l( au x v ou t )= 0.1uf , i o( aux o ut ) = 0 a 1 0 1 5 0 1.5vin to 1.5vout c l( 1.5vou t ) = 0 .1uf , i o( 1.5vout ) = 0 a 1 0 1 5 0 us 3.3vin to 3.3vout c l( 3.3vou t ) = 100uf , r l =v i( 3.3vin ) / 1 a 0 . 1 3 auxin to auxo ut c l( au x v ou t ) = 100uf , r l =v i(a u xinin) /0.250a 0 . 1 3 t f output fall times w hen shdn# asserted (card is present) 1.5vin to 1.5vout c l( 1.5vou t ) = 100uf , r l = vi( 1 .5vin ) /0.500a 0 . 1 3 ms 3.3vin to 3.3vout c l( 3.3vou t ) = 0 .1uf , i o( 3.3vout )= 0 a 0 . 1 6 auxin to auxo ut c l( au x v ou t )= 0.1uf , i o( aux o ut ) =0 a 0 . 1 6 1.5vin to 1.5vout c l( 1.5vou t ) = 0 .1uf , i o( 1.5vout ) =0 a 0 . 1 6 3.3vin to 3.3vout c l( 3.3vou t ) = 100uf , r l =v i( 3.3vin ) /1a 0 . 1 6 auxin to auxo ut c l( au x v ou t ) = 100uf , r l =v i(a u xinin) /0.250a 0 . 1 6 t pd( on) t u rn on propagation delay 1.5vin to 1.5vout c l( 1.5vou t ) = 100uf , r l = vi( 1 .5vin ) /0.500a 0 . 1 6 ms -12-
W83L351 series 9. functional truth tables truth table for voltage outputs vol t a ges input s (1 ) logic inputs voltage outputs (2 ) auxin 3.3vin 1.5vin shdn# st by# cp# (4 ) auxout 3.3vout 1.5vout mode (3 ) o f f x x x x x o f f o f f o f f o f f o n o f f o f f 1 1 x o f f o f f o f f o f f o n o n o n 1 0 0 o f f o f f o f f off (5) o n o n o n 1 0 x o f f o f f o f f off (6) o n x x 0 x x g n d g n d g n d shutdown o n x x 1 x 1 g n d g n d g n d n o c a r d o n o n o n 1 0 0 o n o f f o f f s t a n d b y on on on means the respective input voltage is higher t han its turn on threshold voltage; otherw i se, the voltage is off (for aux input, off means the voltage is close to zero volt). (2) for output voltages, on means the respective pow er sw itch is turned on so the input voltage is connected to the output; off means the pow er sw itch and its output discharge fet are both off; gnd means the pow er sw itch is off but the output discharge fet is on so the voltage on the output is pulled dow n to 0 v. (3) m ode assigns each set of input conditions and respective output voltage results to a different name. these modes are referred to as input conditions in the follow i ng truth table for logic outputs . (4) cp# = cpusb# and cppe# equal to 1 w hen both cpusb# and c ppe# signals are logic high, or equal to 0 w hen either cpusb# or cppe# is low . (5) stby # is asserted (logic low ) prior to the card being present. (6) stby # is asserted (logic low ) prior to the voltage inputs being present. (7) the card is inserted prior to the removal of the primary or se condary pow er (either 3.3vin or 1.5vin or both) at the input of the expresscard pow er sw itch, then only the prim ary and secondary pow er (both 3.3vout and 1.5vout) are removed and the aux iliary pow er is sent to the ex presscard slot. publ i c at i on dat e : jul y 5, 2007 -13- revision 1.10
W83L351 series truth table for logic outputs input conditions logic outputs mode sysrst # rclken (1 ) perst # rclken (2 ) off shutdown no card standby x x 0 0 0 hi - z 0 1 0 0 0 0 1 hi - z 1 1 card inserted 1 0 0 0 (1) rclken as a logic input in this column. rclken is an i/o pin and it can be driven low externally , left open, or connected to high-impedance terminals, such as the gate of a mosfet. it must not be driven high externally . (2) rclken as a logic output in this column. -14-
W83L351 series 10. typical operating waveforms fig.1 output voltage when card is inserted fig.2 rclken and perst# voltage during pow e r up ch1 cppe# ch2 3.3vout ch3 1.5vout ch4 auxout ch1 3.3vout ch2 rclken ch3 perst# publ i c at i on dat e : jul y 5, 2007 -15- revision 1.10
W83L351 series fig.3 rclken and perst# voltage during pow e r dow n fig.4 perst# asserted by sysrst# when pow e r is on ch1 auxout ch2 rclken ch3 perst# ch1 sysrst# ch2 perst# -16-
W83L351 series fig.5 perst# de-asserted by sysrst# when pow e r is on fig.6 output voltage when 3.3vin is remov e d ch1 sysrst# ch2 perst# ch1 3.3vin ch2 3.3vout ch3 1.5vout ch4 auxout publ i c at i on dat e : jul y 5, 2007 -17- revision 1.10
W83L351 series fig.7 output voltage when 1.5vin is remov e d fig.8 oc# response when auxout pow e r into a short ch1 1.5vin ch2 3.3vout ch3 1.5vout ch4 auxout ch1 oc# ch2 auxout -18-
W83L351 series fig.9 oc# response when 3.3vout pow e r into a short fig.10 oc# response when 1.5vout pow e r into a short ch1 oc# ch2 1.5vout ch1 oc# ch2 3.3vout publ i c at i on dat e : jul y 5, 2007 -19- revision 1.10
W83L351 series 11. expresscard timi ng diagrams t p d m i n max u nits a s y s t e m dependent b 100 us c 10 ms d 1 0 0 us e 1 20 ms fig.12 host pow e r is on prior to card insertion (note.2) fig.11 card present before host pow e r (note.1) t p d m i n max u nits a 100 us b 10 ms c 1 20 ms -20-
W83L351 series publ i c at i on dat e : jul y 5, 2007 -21- revision 1.10 fig.13 host sy stem in standby prior to card insertion t p d m i n max u nits a s y s t e m dependent b l o a d dependent c 500 ns d 500 ns fig.14 host controlled pow e r dow n (note.3)
W83L351 series -22- t p d m i n max u nits a s y s t e m dependent b s y s t e m dependent c l o a d dependent d 500 ns e 500 ns fig.15 controlled pow e r dow n when shdn# asserted (note.4) t p d m i n max u nits a l o a d dependent b 500 ns c 500 ns fig.16 surprise card remov a l
W83L351 series note.1: according to the electrical specificati ons of expresscard standard, the minimum propagation delay time of e (power stable to perst# inactive) is 1ms. note.2: rclken could be treated as a power good signal when card power is over 86% of nominal voltage. note.3: the propagation delay time of c is sysrst # assertion to perst# assertion. the propagation delay time of d is card power is under 86% of nominal voltage to rclken de-assertion. note 4: rclekn de-assertion is prior to perst# a ssertion when card power lost in any situation. publ i c at i on dat e : jul y 5, 2007 -23- revision 1.10
W83L351 series 12. package dimension W83L351g - tssop20 -24-
W83L351 series W83L351yg - qfn20, thermal pad dimension: 2.0mm x 2.0mm publ i c at i on dat e : jul y 5, 2007 -25- revision 1.10
W83L351 series W83L351ycg - qfn20, thermal pad dimension: 2.7mm x 2.7mm -26-
W83L351 series ? taping specification 20 pin tssop package 20 pin qfn package publ i c at i on dat e : jul y 5, 2007 -27- revision 1.10
W83L351 series 13. ordering information part number package t ype suppl ied as production flow W83L351g 20pin tssop (pb-free package) e shape: 74 units/tube t shape: 2,500 units /t&r commercial, 0 L L -28-
W83L351 series 14. top marking specification W83L351g 212345678 606xara winbond 351yg 636xarb winbond 351ycg 636xarb 1 st line: winbond ? company name 2 nd line: 351yg/351ycg ? the part number 3 rd l i n e : t r a c k i n g c o d e 6 3 6 x arb 636 : packages assembled in year 06?, week 36 x : assembly house id arb : the ic version left line: winbond logo 1 st line: W83L351g ? the part number 2 nd line: chip lot no 3 rd l i n e : t r a c k i n g c o d e 6 0 6 x ara 606 : packages assembled in year 06?, week 06 x : assembly house id ara : the ic version publ i c at i on dat e : jul y 5, 2007 -29- revision 1.10
W83L351 series -30- important notice winbond products are not designed, intended, authorized or w a rranted for use as components in sy stems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications w h erein failure of winbond products could result or lead to a situation w h erein personal injury , death or sev ere property or env i ronmental damage could occur. winbond customers using or selling these products for use in such applications do so at their ow n risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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